View CXD1179_14849.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXD1179Q
8-bit 35MSPS Video A/D Converter with Clamp Function
Description The CXD1179Q is an 8-bit CMOS A/D converter for video with synchronizing clamp function. The adoption of 2 step-parallel method achieves ultra-low power consumption and a maximum conversion speed of 35MSPS. Features * Resolution: 8-bit 1/2LSB (DL) * Maximum sampling frequency: 35MSPS * Low power consumption: 80 mW (at 35MSPS typ.) (reference current excluded) * Synchronizing clamp function * Clamp ON/OFF function * * * * * * Reference voltage self bias circuit Input CMOS compatible 3-state TTL compatible output Single 5V power supply Low input capacitance: 8 pF Reference impedance: 330 (typ.) 32 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage VDD 7 * Reference voltage VRT, VRB VDD + 0.5 to VSS - 0.5 * Input voltage VIN VDD + 0.5 to VSS - 0.5 (Analog) * Input voltage VI VDD + 0.5 to VSS - 0.5 (Digital) * Output voltage VO (Digital) * Storage temperature Tstg
V V V V
VDD + 0.5 to VSS - 0.5 V
Applications Wide range of applications that require high-speed A/D conversion such as TV and VCR. Structure Silicon gate CMOS IC
-55 to +150
C
Recommended Operating Conditions * Supply voltage AVDD, AVSS 4.75 to 5.25 V DVDD, DVSS | DVSS - AVSS | 0 to 100 mV * Reference input voltage VRB 0 and above V VRT 2.7 and below V * Analog input VIN 1.8 Vp-p above * Clock pulse width Tpw1, Tpw0 13 ns (min) to 1.1 s (max) * Operating ambient temperature Topr -40 to +85 C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E91Z07G86-TE
CXD1179Q
Block Diagram
DVss 28 OE 30 Reference supply DVss 31 D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) 1 23 AVss 2 3 4 5 6 7 8 16 AVDD DVDD 10 TEST (DVDD) 11 CLK 12 Clock generator Upper data latch Lower encoder (4 BIT) Lower sampling comparator (4 BIT) Lower data latch Lower encoder (4 BIT) Lower sampling comparator (4 BIT) 22 AVss 21 VIN 20 AVDD 19 AVDD 18 VRT 17 VRTS 25 VRBS 24 VRB
Upper encoder (4 BIT)
Upper sampling comparator (4 BIT)
TEST (OPEN)
9
15 CLP 14 TEST (VDD or Vss) 13 TEST (VDD or Vss)
NC 32
29 CLE
27 CCP
26 VREF
--2--
CXD1179Q
Pin Description Pin No. Symbol Equivalent circuit Description
1 to 8
D0 to D7
Di
D0 (LSB) to D7 (MSB) output
DVDD
9
TEST
9
Leave open during normal usage.
DVSS
10
DVDD
Digital +5 V
DVDD
12
CLK
12
Clock input
DVSS
DVDD
11
11, 13, 14
TEST
13 14
Fix Pin 11 to VDD, Pins 13 and 14 to VDD or VSS during normal usage.
DVSS
--3--
CXD1179Q
Pin No.
Symbol
Equivalent circuit
DVDD
Description
15
CLP
15
Inputs clamp pulse to Pin 15 (CLP). Clamps the signal voltage during Low interval.
DVSS
16, 19, 20
AVDD
AVDD
Analog +5 V
17
VRTS
17
Generates about +2.6 V when shorted with VRT.
18
VRT
AVDD
Reference voltage (top)
18
24
24
VRB
AVSS
Reference voltage (bottom)
AVDD
21
VIN
21
Analog input
AVSS
22, 23
AVSS
AVSS
Analog ground
25
VRBS
25
Generates about +0.6 V when shorted with VRB.
--4--
CXD1179Q
Pin No.
Symbol
Equivalent circuit
Description
AVDD
26
VREF
26
Clamp reference voltage input. Clamps so that the reference voltage and the input signal during clamp interval are equal.
AVSS
AVDD
27
CCP
27
Integrates the clamp control voltage. The relationship between the changes in CCP voltage and in VIN voltage is positive phase.
AVSS
28, 31
DVSS
Digital ground
DVDD
29
CLE
29
DVSS
CLAMP PULSE
The clamp function is enabled when CLE = Low. The clamp function is set to off and the converter functions as a normal A/D converter when CLE = High. The clamp pulse can be measured by connecting CLE to DVDD through a several hundred resistor.
DVDD
30
OE
30
Data is output when OE = Low. Pins D0 to D7 are at high impedance when OE = High.
DVSS
32
NC
NC pin
--5--
CXD1179Q
Digital Output The following table shows the relationship between analog input voltage and digital output code.
Input signal voltage VRT : : : : VRB
Step 0 : 127 128 : 255
Digital output code MSB LSB 11111 : 10000 01111 : 00000 111 000 111 000
TPW1
TPW0
Clock 2V
Analog input
N
N+1
N+2 N-1
N+3
N+4 N+1
Data output 2V
N-3
N-2
N
Td = 13ns : Analog signal sampling point
Timing Chart I.
tr = 4.5ns
tf = 4.5ns 5V 90%
OE input
2.5V 10% tPLZ tPZL 0V VOH
output 1 10% tPHZ tPZH 90% output 2
1.3V VOL ( DVSS) VOH ( DVDD) 1.3V VOL
Timing Chart II.
--6--
CXD1179Q
Electrical Characteristics Analog characteristics Item Symbol (Fc = 35MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 C) Conditions VDD = 4.75 to 5.25 V Ta = -40 to +85 C VIN = 0.5 to 2.5 V fIN = 1 kHz ramp Envelope Potential difference to VRT Potential difference to VRB End point -60 +55 Min. Typ. Max. Unit
Conversion speed
Fc
0.5
35
MSPS
Analog input band width (-1 dB) Offset voltage1 Integral non-linearity error
BW EOT EOB EL
25 -40 +75 +0.5 0.3 -20 +95 +1.3 -1.0 0.5
MHz mV
LSB % deg ps ns
Differential non-linearity error ED Differential gain error Differential phase error Aperture jitter Sampling delay Clamp offset voltage2 Clamp pulse delay DG DP NTSC 40 IRE mod ramp Fc = 14.3MSPS
1 0.5 30 2
taj tsd
Eoc VIN = DC, PWS = 3 s VREF = 0.5 V VREF = 2.5 V -20 -30
0 -10 25
+20 +10
mV ns
tcpd
1 The offset voltage EOB is a potential difference between VRB and a point of position where the voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from "00000000" to "00000001". EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to 1/2LSB of the voltage when the output data changes from "11111111" to "11111110". 2 Clamp offset voltage varies individually. When using with R, G, B 3 channels, color sliding may be generated.
--7--
CXD1179Q
DC characteristics Item Supply current Reference pin current Analog input capacitance Reference resistance (VRT to VRB) Self-bias I Self-bias II Digital input voltage Symbol IDD IREF CIN RREF VRB1 VRT1 - VRB1 VRT2 VIH VIL IIH IIL IOH Digital output current IOL IOZH IOZL
(Fc = 35MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 C) Conditions Fc = 35MSPS NTSC ramp wave input 4.5 VIN = 1.5 V + 0.07 Vrms 230 Shorts VRB and VRBS Shorts VRT and VRTS VRB = AGND Shorts VRT and VRTS VDD = 4.75 to 5.25 V Ta = -40 to +85 C VIH = VDD VDD = max OE = VSS VDD = min OE = VDD VDD = max VIL = 0 V VOH = VDD - 0.5 V -1.1 VOL = 0.4 V VOH = VDD VOL = 0 V 3.7 -2.5 6.5 16 16 0.52 1.96 2.13 3.5 0.5 5 5 Min. Typ. 16 6.1 8 330 0.56 2.10 2.33 440 0.60 2.24 2.53 Max. 22 8.7 Unit mA mA pF V V V
Digital input current
A
mA
A
Timing Item Output data delay Symbol TDL
(Fc = 35MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 C) Conditions With TTL 1 gate and 10 pF load VDD = 4.75 to 5.25 V Ta = -40 to +85 C RL = 1 k, CL = 15 pF OE = 5 V 0 V VDD = 4.75 to 5.25 V Ta = -40 to +85 C RL = 1 k, CL = 15 pF OE = 0V 5 V VDD = 4.75 to 5.25 V Ta = -40 to +85 C Fc = 14MSPS, CIN = 10 F for NTSC wave Min. 7 Typ. 13 Max. 18 Unit ns
Tri-state output enable time
tPZH tPZL
5
8
14
ns
Tri-state output disable time Clamp pulse width1
tPHZ tPLZ tcpw
4
6.5
11
ns
1.75
2.75
3.75
s
1 The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75 kHz for NTSC) for other processing systems to equal the values for NTSC.
--8--
CXD1179Q
Electrical Characteristics Measurement Circuit Integral non-linearity error Differential non-linearity error Offset voltage
}
S2 S1
Tri-state output measurement circuit measurement circuit
+V
S1: ON IF A < B S2: ON IF B > A
Measurement point
DVDD
RL
-V AB COMPARATOR A8 B8 to to A1 B1 A0 B0
To output pin
VIN
8 DUT CXD1179Q "0" CLK (35MHz)
8
BUFFER
CL
RL
DVM
"1" 8 000 * * * 00 to 111 * * * 10 Note) CL includes capacitance of the probe and others.
CONTROLLER
Maximum operational speed Differential gain error Differential phase error
}
measurement circuit
2.5V Fc - 1kHz
ERROR RATE CX20202A-1
S.G.
0.5V
H.P.F 1 2 VECTOR SCOPE
COUNTER
1 AMP
100
VIN CXD 1179Q
2.5V
8
TTL ECL
8 620 -5.2V
10bit D/A
2
40 IRE MODULATION BURST
NTSC
IAE
SIGNAL SOURCE
CLK
0 -40 0.5V SYNC
620 TTL -5.2V
D.G D.P.
S.G. (CW)
FC
ECL
Digital output current measurement circuit
2.5V 0.5V
VDD VRT VIN VRB CLK OE GND VOL
IOL
2.5V 0.5V + -
VDD VRT VIN VRB CLK OE GND VOH
IOH
+ -
--9--
CXD1179Q
Vi (1)
Vi (2)
Vi (3)
Vi (4)
Analog input
External clock
Upper comparators block
S (1)
C (1)
S (2)
C (2)
S (3)
C (3)
S (4)
C (4)
Upper data
MD (0)
MD (1)
MD (2)
MD (3)
Lower reference voltage
RV (0)
RV (1)
RV (2)
RV (3)
Lower comparators A block
S (1)
H (1)
C (1)
S (3)
H (3)
C (3)
Lower data A
LD (-1)
LD (1)
Lower comparators B block
H (0)
C (0)
S (2)
H (2)
C (2)
S (4)
H (4)
Lower data B
LD (-2)
LD (0)
LD (2)
Digital output
Out (-2)
Out (-1)
Out (0)
Out (1)
Timing Chart 3 Operation (See Block Diagram and Timing Chart 3) 1. The CXD1179Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2 lower comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT - VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower data. VRTS and VRBS pins serve for the self generation of VRT (Reference voltage top) and VRB (Reference voltage bottom). --10--
CXD1179Q
2. This IC uses an offset cancel type comparator and the comparator operates synchronously with an external clock. These modes are respectively indicated on the timing chart with S, H, C symbols. That is, the comparator performs input sampling (auto zero) mode, input hold mode and comparison mode using the external clock. 3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled with the falling edge of the first clock by means of the upper comparator block and the lower comparator A block. The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock. Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock. Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.
Operation Notes 1. Power supply and ground To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog power supply pins, use a ceramic capacitor of about 0.1 F set as close as possible to the pin to bypass to the respective grounds. 2. Analog input Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by inserting a resistance of about 100 in series between the amplifier output and A/D input. 3. Clock input The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. Reference input Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins to analog ground, by means of a capacitor about 0.1 F, the stable characteristics of the reference voltage are obtained. By shorting VRT and VRTS, VRB and VRBS, the self-bias function that generates VRT = about 2.6 V and VRB = about 0.6 V, is activated. 5. Timing Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 13ns. 6. OE pin By connecting OE to DVSS output mode is obtained. By connecting OE to DVDD high impedance is obtained. --11--
CXD1179Q
Application Circuit (1) When clamp is used (self bias used)
+5V (Digital) ACO4 CLOCK IN OPEN CLAMP PULSE IN CK LATCH Q 0.01 +5V (Analog) 17 18 19 VIDEO IN 10 20 75 21 0.1 10P 22 23 0.01 +5V (Analog) VREF 20k GND (Analog) 24 25 26 27 28 0.01 GND (Digital) 29 30 31 32 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D7 D6 D5 D4 D3 D2 D1 D0 0.1
The clamp pulse is latched by the sampling clock of ADC, but that is not necessary for basic clamp operation. However, slight small beat may be generated as vertical sag according to the relationship between the sampling frequency and the clamp pulse frequency. At such time, the latch circuit is effective in this case.
--12--
CXD1179Q
(2) Digital clamp (self bias used)
+5V (Digital) ACO4 CLOCK IN CLAMP PULSE IN 16 0.01 +5V (Analog) 17 18 19 VIDEO IN 10 20 75 21 0.1 10P 22 23 0.01 24 25 26 27 28 29 30 31 32 DAC, PWM, etc. GND (Digital) GND (Analog) 15 14 13 12 11 10 9 0.1 OPEN 8 7 6 5 4 3 2 1 Latch, Subtracter, Comparator, etc. Clamp Level setting data
(3) When clamp is not used (self bias used)
+5V (Digital) ACO4 CLOCK IN OPEN 16 0.01 +5V (Analog) 17 18 19 VIDEO IN 20 75 21 0.1 10P 22 23 0.01 24 25 26 27 28 29 30 31 32 4 3 2 1 D3 D2 D1 D0 15 14 13 12 11 10 9 8 7 6 5 D7 D6 D5 D4 0.1
GND (Digital) +5V (Digital) GND (Analog)
--13--
CXD1179Q
Package Outline
Unit : mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15
0.1
25
16
32
9
+ 0.2 0.1 - 0.1
1 0.8 + 0.15 0.3 - 0.1
8 + 0.1 0.127 - 0.05 0 to 10
0.24
M
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g
--14--
0.50
(8.0)

▲Up To Search▲

Price & Availability of CXD1179

	To Download CXD1179 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .